Integrated circuit speeds continue to increase and the amount of data processed and communicated continues to increase to meet the demands of system applications. As data volume increases, the industry continues to develop higher bandwidth communications links and larger memory sizes to prevent data communication bottlenecks and to accommodate the increased data requirements. The trends, of increasing data volume and larger memory sizes, are expected to continue into the future.
Typically, an electrical system includes a number of circuits that communicate with one another to perform system applications. The circuits can be on the same integrated circuit chip or on separate integrated circuit chips. Often, the electrical system includes one or more controllers, such as a micro-processor, and one or more memory devices, such as a random access memory (RAM) device. The RAM can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), and graphics DDR-SDRAM (GDDR-SDRAM). Also, the RAM can be any suitable generation of RAM, such as first, second, third, or higher generations of RAM. The controller communicates with the memory to store data and to read the stored data.
Generally, the RAM needs to read, write, and communicate data at ever increasing speeds to handle the ever increasing data volume. In one approach, the operation frequency of the RAM is increased. In another approach, DDR-SDRAM reads and writes data on the falling edge and on the rising edge of the clock signal. Also, each higher generation of RAM includes features and improvements, such as features and improvements that increase speed, not found in lower generations.
GDDR-SDRAM is used in graphics applications, which have high data volume demands. In a proposed version of fifth-generation GDDR-SDRAM (GDDR5-SDRAM), the data synchronous clock, referred to as the write data strobe clock signal (WDQS), is a continuously running clock signal. The write data strobe clock signal no longer includes post-amble or pre-amble as it did in previous generations of GDDR-SDRAM. This implies that input registers receive data and latch-in the received data at each clock cycle, whether the received data is valid data or invalid data. However, only the valid data may be written into the memory array of the RAM.
For these and other reasons there is a need for the present invention.